Nanoscale CMOS has brought many high speed applications to the consumer thanks to the computing power that can be leveraged from modern signal processors. Unfortunately, the intrinsic analog properties of CMOS transistors generally do not follow the improvements of their digital counterparts. CMOS transistor parameters like output impedance, supply versus threshold ratio, or intrinsic gain typically worsen with the advance of the CMOS technological nodes.
One example of a relevant application field is digital radio transmitters. Modern communication schemes can impose strict requirements on radio transmitters. Transmitters operating at RF often have to combine strict requirements such as RF bandwidth, linearity, and out-of-band noise while maintaining a high efficiency. As a result, the porting of an analog RF transmitter from one technological node to another is complicated and thus slow and costly. Thus, it is often beneficial to design transmitters to have a reduced amount of analog circuitry. In addition, it is generally desirable for radio transmitters to be easily scalable with the advancement of CMOS technologies.
To address problems that can accompany analog RF transmitters, a new family of RF transmitters, digital transmitters (also referred to as RF-DACs or Direct Digital RF Modulators, DDRM), has been adopted. The digital transmitters feature predominantly digital circuitry which is better suited for advanced CMOS technology and which scales much better with the various CMOS technological nodes. In contrast to their analog counterpart, the performance of digital transmitters intrinsically improves with the scaling of CMOS technology.
The first digital transmitters were based on a polar architecture, in which a phase modulated local oscillator (LO) signal is fed to a multitude of DDRM units and amplitude modulation is performed by enabling or disabling (switching on or off) these DDRM unit amplifiers and then combining their output power to form a modulated RF analog signal. Later, Cartesian DDRM architectures consisting of two such digital amplitude modulators, for modulating the in-phase (I) and the quadrature (Q) signals with the respective LO phases, were also adopted in digital transmitters. The outputs of these two digital amplitude modulators are summed before being fed to the antenna for transmission.
Similar to a DAC, a digital power amplifier transforms digital input amplitude code into amplitude-modulated RF carrier. The digital-to-analog conversion unavoidably generates clock aliasing at multiples of the clock frequency.
In order to reduce the effect of aliasing, the sampling rate generally needs to be increased. To reduce the amount of quantization noise it is helpful to increase the accuracy. Although the total amount of quantization noise generally only relates to the digital-to-analog resolution/accuracy, the increase of sampling rate spreads the quantization noise into a wider bandwidth, so the quantization noise density is reduced.
A discrete-time input sample stream can be upsampled/interpolated with time alignment utilizing the addition of randomized high frequency noise. The upsampling mechanism can make use of a second order interpolator. The process can involve taking the derivative of the discrete-time input sample stream, thereby effectively providing another order of interpolation over a conventional interpolator. Before outputting the interpolated signal, an integrator can take the integral of the interpolated samples. Any processing performed between the derivative and integrator blocks can effectively provide an additional order of interpolation. High frequency noise (i.e. dithering) can be added to the differentiated samples in order to eliminate the spectral regrowth spurs that could otherwise appear in the output after rounding. Delay alignment can be performed on the differentiated samples in order to time align both phase/frequency and amplitude samples that are processed on different paths.
A digital quadrature rate converter and an oversampling interpolator can be presented for a DDRM. Digital quadrature modulation data can be received at one clock rate and oversampled digital quadrature modulation data can be provided at a higher clock rate. Rate conversion and oversampled interpolation can be used to accommodate systems with multiple clock frequencies and to generate modulation signals with low distortion. In this cascaded multi-rate approach all data is typically upsampled to the highest clock frequency.
The above-mentioned solutions typically end up upsampling all data to the highest clock frequency at the cost of higher power consumption for the digital circuits.
Hence, there is a need for a circuit with enhanced out-of-band spectral purity wherein these drawbacks are reduced or overcome.